Field of the Invention
The present invention relates to an integrated semiconductor circuit, in particular a semiconductor memory, having a semiconductor chip, a housing, which accommodates the semiconductor chip, and a lead frame that connects the contact areas of the semiconductor chip with external terminals of the integrated semiconductor circuit. First regions of the lead frame, which are connected to the contact areas, and second regions of the lead frame, which are connected to the external terminals, are located essentially in an identical plane.
For semiconductor memories, for example 16 megabit semiconductor memories, it is possible to use so-called TSOP housings (TSOP=Thin small outline package) with a housing thickness of about 1 mm or else so-called SOJ housings (SOJ=Small Outline J Bend) with a housing thickness of about 2.5 mm. If the housings are constructed in LOC technology (LOC=Lead-On-Chip), then housing connections are not provided on the housing centrosymmetrically or centrically. The same also applies to the routing of the conductors of the lead frame which connect respective contact areas or pads of the semiconductor chip to the housing connections. In this case, the contact areas serve for the mechanical fixing of the semiconductor chip to the lead frame, while the electrical connection is effected via, for example, gold wires to bonding pads.
If the semiconductor chip happens to be very much smaller than the housing, which may be the case when an existing housing is intended to be used for a considerably smaller semiconductor chip, then the housing has relatively large regions in which no semiconductor chip is present.
FIG. 3 shows a plan view of a prior art integrated semiconductor circuit, the cross section of which is illustrated in FIG. 4. This integrated semiconductor circuit comprises a semiconductor chip 1, contact areas 2 arranged thereon, conductors 3 of a lead frame 4, which are mechanically connected to the contact areas 2, bonding wires 10 made of gold, for example, which serve the purpose of electrical connection between the conductors 3 and electrical contacts ("bonding pads") 9, as well as a housing 5 made of a molding compound, for example epoxy resin. In order to simplify the illustration, the contact areas 2 are only illustrated in FIG. 4, which, incidentally, shows the conductors 3 as if the housing 5 were omitted. As is evident, then, from FIGS. 3 and 4, in this case the relatively small semiconductor chip 1 is accommodated in the housing 5 which is large in comparison therewith. There is thus a zone A, in which the semiconductor chip 1 and the housing 5 are present in a side section, whereas in zones B, which are outside the region of the semiconductor chip 1, only the conductors 3 of the lead frame 4 and also the molding compound of the housing 5 are present. Although FIGS. 3 and 4 show an example in which the semiconductor chip 1 is arranged centrically in the housing 5, these zones B located to the left and right of the semiconductor chip 1 in FIGS. 3 and 4 are relatively large. In the case of a noncentric arrangement of the semiconductor chip 1 in the housing 5, that is to say if the semiconductor chip 1 is accommodated in the housing 5 in a manner shifted to the left in FIGS. 3 and 4, one of these zones B, the zone B located on the right in FIGS. 3 and 4 in the example given, would gain even greater dimensions.
This means that, in the integrated semiconductor circuit illustrated, the semiconductor chip 1 and the housing 5 are present in the zone A, whereas the housing 5 and the conductors 3 are present in the zones B. The thermal expansion coefficients of the semiconductor material of the semiconductor chip 1 and of the conductor 3 are relatively close to one another. However, the thermal expansion coefficient of the molding compound of the housing 5 differs considerably from the thermal expansion coefficients of the semiconductor material and of the conductor. As a result, the integrated semiconductor circuit is thermally balanced in zone A ("balanced package"), whereas such thermal balancing is not present in zones B ("non-balanced package"). Flexure thus occurs in the integrated semiconductor circuit, this being indicated by dashed lines in FIG. 4. Flexure of this type is greater, the smaller the thickness of the housing 5 is and the further the zones B extend beyond the zone A. Flexure of this type is extremely undesirable for the mounting of the integrated semiconductor circuit since it causes alteration of the housing dimensions of the integrated semiconductor circuit and, possibly, loss of the coplanarity of the integrated semiconductor circuit with other components. This may have an adverse effect both on the mechanical and on the electrical properties of the product.
Patent Abstracts of Japan 18(643)(E1640) and JP A 6252333 describe a semiconductor configuration having a semiconductor chip, a lead frame and a surrounding housing. The semiconductor chip is applied to a chip island of the lead frame. The connection fingers are formed in such a way that, in an alternating manner, first of all parts of the connection fingers are accessible on the top side of the semiconductor component and then parts are accessible on the underside of the semiconductor component. There are, moreover, connection fingers which are routed outward on the side of the housing. A large pitch spacing of the connection fingers can be obtained in this way.
Patent Abstracts of Japan 16(014)(E1154) and JP A 3235360 describe a semiconductor configuration having a semiconductor chip, a lead frame and a surrounding housing. In this case, the first ends of the connection fingers are fixed on a top side of the semiconductor chip according to the lead on chip principle. The regions of the connection fingers which are situated within the housing have a stepped form, with the result that they penetrate through the housing in the central plane. By virtue of the step in the connection fingers, the semiconductor chip can be fitted approximately in the central plane of the housing.